Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs
This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysi...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9094170/ |
| _version_ | 1818417321062957056 |
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| author | Shantanu Mehta Daniel O'Hare Vincent O'Brien Eric Thompson Brendan Mullane |
| author_facet | Shantanu Mehta Daniel O'Hare Vincent O'Brien Eric Thompson Brendan Mullane |
| author_sort | Shantanu Mehta |
| collection | DOAJ |
| description | This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ~ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology. |
| first_indexed | 2024-12-14T12:04:55Z |
| format | Article |
| id | doaj.art-ab791ba366b84c658d64d06fc58078d0 |
| institution | Directory Open Access Journal |
| issn | 2644-1225 |
| language | English |
| last_indexed | 2024-12-14T12:04:55Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj.art-ab791ba366b84c658d64d06fc58078d02022-12-21T23:01:54ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252020-01-011344710.1109/OJCAS.2020.29948389094170Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCsShantanu Mehta0Daniel O'Hare1Vincent O'Brien2Eric Thompson3Brendan Mullane4Department of Electronic and Computer Engineering, Circuits and Systems Research Centre, University of Limerick, Limerick, IrelandMCCI, Tyndall National Institute, Cork, IrelandDepartment of Aerospace, Mechanical and Electronic Engineering, Institute of Technology Carlow, Carlow, IrelandDepartment of Desgin, Analog Devices, Limerick, IrelandDepartment of Electronic and Computer Engineering, Circuits and Systems Research Centre, University of Limerick, Limerick, IrelandThis paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ~ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.https://ieeexplore.ieee.org/document/9094170/Tri-levelcurrent-steeringDACsthermal noiseDNLINL |
| spellingShingle | Shantanu Mehta Daniel O'Hare Vincent O'Brien Eric Thompson Brendan Mullane Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs IEEE Open Journal of Circuits and Systems Tri-level current-steering DACs thermal noise DNL INL |
| title | Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs |
| title_full | Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs |
| title_fullStr | Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs |
| title_full_unstemmed | Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs |
| title_short | Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs |
| title_sort | analysis and design of a tri level current steering dac with 12 bit linearity and improved impedance matching suitable for ct adcs |
| topic | Tri-level current-steering DACs thermal noise DNL INL |
| url | https://ieeexplore.ieee.org/document/9094170/ |
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