Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author r...

Full description

Bibliographic Details
Main Authors: C. Senthilpari, K. Diwakar, Kumar Munusamy, J. Sheela Francisca
Format: Article
Language:English
Published: Elsevier 2017-02-01
Series:Engineering Science and Technology, an International Journal
Subjects:
RLC modelling
32 bit adder
Shannon theorem
Interconnect parameter
Power factor
Online Access:http://www.sciencedirect.com/science/article/pii/S2215098616303913

Internet

http://www.sciencedirect.com/science/article/pii/S2215098616303913

Similar Items