Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit
The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author r...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Elsevier
2017-02-01
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| Series: | Engineering Science and Technology, an International Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098616303913 |
| _version_ | 1818408533768536064 |
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| author | C. Senthilpari K. Diwakar Kumar Munusamy J. Sheela Francisca |
| author_facet | C. Senthilpari K. Diwakar Kumar Munusamy J. Sheela Francisca |
| author_sort | C. Senthilpari |
| collection | DOAJ |
| description | The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed-Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC interconnect parameter such as capacitive impedance, inductive impedance, power factor sin ϕ, tan ϕ for applying frequency. The 32 bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin ϕ and tan ϕ. |
| first_indexed | 2024-12-14T09:45:15Z |
| format | Article |
| id | doaj.art-abb2c1e49e6c4fb8b50d5940b7386ef0 |
| institution | Directory Open Access Journal |
| issn | 2215-0986 |
| language | English |
| last_indexed | 2024-12-14T09:45:15Z |
| publishDate | 2017-02-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Engineering Science and Technology, an International Journal |
| spelling | doaj.art-abb2c1e49e6c4fb8b50d5940b7386ef02022-12-21T23:07:39ZengElsevierEngineering Science and Technology, an International Journal2215-09862017-02-01201354010.1016/j.jestch.2016.08.012Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuitC. Senthilpari0K. Diwakar1Kumar Munusamy2J. Sheela Francisca3Faculty of Engineering, Multimedia University, 63100, Jalan Multimedia, Cyberjaya, Selangor, MalaysiaVeltech University, Department of Electronic and Communication Engineering, Avadi, Chennai, Tamil NaduUsains Infotech Sdn Bhd, Koridor Utara-NTDC, Plot No 36, Bayan Lepas Industrial Estate, Phase 4, 11900 Bayan Lepas, Penang, MalaysiaFaculty of Engineering, Multimedia University, 63100, Jalan Multimedia, Cyberjaya, Selangor, MalaysiaThe 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed-Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC interconnect parameter such as capacitive impedance, inductive impedance, power factor sin ϕ, tan ϕ for applying frequency. The 32 bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin ϕ and tan ϕ.http://www.sciencedirect.com/science/article/pii/S2215098616303913RLC modelling32 bit adderShannon theoremInterconnect parameterPower factor |
| spellingShingle | C. Senthilpari K. Diwakar Kumar Munusamy J. Sheela Francisca Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit Engineering Science and Technology, an International Journal RLC modelling 32 bit adder Shannon theorem Interconnect parameter Power factor |
| title | Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit |
| title_full | Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit |
| title_fullStr | Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit |
| title_full_unstemmed | Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit |
| title_short | Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit |
| title_sort | layout parameter analysis in shannon expansion theorem based on 32 bit adder circuit |
| topic | RLC modelling 32 bit adder Shannon theorem Interconnect parameter Power factor |
| url | http://www.sciencedirect.com/science/article/pii/S2215098616303913 |
| work_keys_str_mv | AT csenthilpari layoutparameteranalysisinshannonexpansiontheorembasedon32bitaddercircuit AT kdiwakar layoutparameteranalysisinshannonexpansiontheorembasedon32bitaddercircuit AT kumarmunusamy layoutparameteranalysisinshannonexpansiontheorembasedon32bitaddercircuit AT jsheelafrancisca layoutparameteranalysisinshannonexpansiontheorembasedon32bitaddercircuit |