Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit
The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author r...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2017-02-01
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| Series: | Engineering Science and Technology, an International Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098616303913 |