A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits
As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of criti...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-09-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/12/18/9103 |
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| author | Prathiba Muthukrishnan Sivanantham Sathasivam |
| author_facet | Prathiba Muthukrishnan Sivanantham Sathasivam |
| author_sort | Prathiba Muthukrishnan |
| collection | DOAJ |
| description | As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed. |
| first_indexed | 2024-03-10T00:50:12Z |
| format | Article |
| id | doaj.art-ac64c497229f4304b1754d25a1a08a08 |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-10T00:50:12Z |
| publishDate | 2022-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-ac64c497229f4304b1754d25a1a08a082023-11-23T14:53:02ZengMDPI AGApplied Sciences2076-34172022-09-011218910310.3390/app12189103A Technical Survey on Delay Defects in Nanoscale Digital VLSI CircuitsPrathiba Muthukrishnan0Sivanantham Sathasivam1School of Electronics Engineering, Vellore Institute of Technology, Vellore 632014, Tamil Nadu, IndiaSchool of Electronics Engineering, Vellore Institute of Technology, Vellore 632014, Tamil Nadu, IndiaAs technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.https://www.mdpi.com/2076-3417/12/18/9103nanoscale devicessmall delay defecthidden delay defectVLSI testingtest quality metricat-speed testing |
| spellingShingle | Prathiba Muthukrishnan Sivanantham Sathasivam A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits Applied Sciences nanoscale devices small delay defect hidden delay defect VLSI testing test quality metric at-speed testing |
| title | A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits |
| title_full | A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits |
| title_fullStr | A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits |
| title_full_unstemmed | A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits |
| title_short | A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits |
| title_sort | technical survey on delay defects in nanoscale digital vlsi circuits |
| topic | nanoscale devices small delay defect hidden delay defect VLSI testing test quality metric at-speed testing |
| url | https://www.mdpi.com/2076-3417/12/18/9103 |
| work_keys_str_mv | AT prathibamuthukrishnan atechnicalsurveyondelaydefectsinnanoscaledigitalvlsicircuits AT sivananthamsathasivam atechnicalsurveyondelaydefectsinnanoscaledigitalvlsicircuits AT prathibamuthukrishnan technicalsurveyondelaydefectsinnanoscaledigitalvlsicircuits AT sivananthamsathasivam technicalsurveyondelaydefectsinnanoscaledigitalvlsicircuits |