Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications
The existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memory bottlenecks. As an alternative, compute-in-memory (CIM) technology has been emerging. Among various CIM device candidates, split-gate NOR flash offers advantages su...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-09-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/14/9/1753 |
| _version_ | 1797578828714868736 |
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| author | Chan-Gi Yook Jung Nam Kim Yoon Kim Wonbo Shim |
| author_facet | Chan-Gi Yook Jung Nam Kim Yoon Kim Wonbo Shim |
| author_sort | Chan-Gi Yook |
| collection | DOAJ |
| description | The existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memory bottlenecks. As an alternative, compute-in-memory (CIM) technology has been emerging. Among various CIM device candidates, split-gate NOR flash offers advantages such as a high density and low on-state current, enabling low-power operation, and benefiting from a high level of technological maturity. To achieve high energy efficiency and high accuracy in CIM inference chips, it is necessary to optimize device design by targeting low power consumption at the device level and surpassing baseline accuracy at the system level. In split-gate NOR flash, significant factors that can cause CIM inference accuracy drop are the device conductance variation, caused by floating gate charge variation, and a low on-off current ratio. Conductance variation generally has a trade-off relationship with the on-current, which greatly affects CIM dynamic power consumption. In this paper, we propose strategies for designing optimal devices by adjusting oxide thickness and other structural parameters. As a result of setting <i>T<sub>ox,FG</sub></i> to 13.4 nm, <i>T<sub>IPO</sub></i> to 4.6 nm and setting other parameters to optimal points, the design achieves erase on-current below 2 μA, program on-current below 10 pA, and off-current below 1 pA, while maintaining an inference accuracy of over 92%. |
| first_indexed | 2024-03-10T22:27:20Z |
| format | Article |
| id | doaj.art-acf3e0071f3243d9a55100d2f0a4914f |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-10T22:27:20Z |
| publishDate | 2023-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-acf3e0071f3243d9a55100d2f0a4914f2023-11-19T12:00:10ZengMDPI AGMicromachines2072-666X2023-09-01149175310.3390/mi14091753Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory ApplicationsChan-Gi Yook0Jung Nam Kim1Yoon Kim2Wonbo Shim3Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul 01811, Republic of KoreaSchool of Electrical and Computer Engineering, University of Seoul, Seoul 02504, Republic of KoreaSchool of Electrical and Computer Engineering, University of Seoul, Seoul 02504, Republic of KoreaDepartment of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul 01811, Republic of KoreaThe existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memory bottlenecks. As an alternative, compute-in-memory (CIM) technology has been emerging. Among various CIM device candidates, split-gate NOR flash offers advantages such as a high density and low on-state current, enabling low-power operation, and benefiting from a high level of technological maturity. To achieve high energy efficiency and high accuracy in CIM inference chips, it is necessary to optimize device design by targeting low power consumption at the device level and surpassing baseline accuracy at the system level. In split-gate NOR flash, significant factors that can cause CIM inference accuracy drop are the device conductance variation, caused by floating gate charge variation, and a low on-off current ratio. Conductance variation generally has a trade-off relationship with the on-current, which greatly affects CIM dynamic power consumption. In this paper, we propose strategies for designing optimal devices by adjusting oxide thickness and other structural parameters. As a result of setting <i>T<sub>ox,FG</sub></i> to 13.4 nm, <i>T<sub>IPO</sub></i> to 4.6 nm and setting other parameters to optimal points, the design achieves erase on-current below 2 μA, program on-current below 10 pA, and off-current below 1 pA, while maintaining an inference accuracy of over 92%.https://www.mdpi.com/2072-666X/14/9/1753compute-in-memory (CIM)NOR flashsplit-gate NOR flashdevice optimizationartificial intelligenceconvolutional neural network |
| spellingShingle | Chan-Gi Yook Jung Nam Kim Yoon Kim Wonbo Shim Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications Micromachines compute-in-memory (CIM) NOR flash split-gate NOR flash device optimization artificial intelligence convolutional neural network |
| title | Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications |
| title_full | Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications |
| title_fullStr | Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications |
| title_full_unstemmed | Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications |
| title_short | Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications |
| title_sort | design strategies of 40 nm split gate nor flash memory device for low power compute in memory applications |
| topic | compute-in-memory (CIM) NOR flash split-gate NOR flash device optimization artificial intelligence convolutional neural network |
| url | https://www.mdpi.com/2072-666X/14/9/1753 |
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