Si‐Based Dual‐Gate Field‐Effect Transistor Array for Low‐Power On‐Chip Trainable Hardware Neural Networks

Si‐Based Dual‐Gate Field‐Effect Transistor Array for Low‐Power On‐Chip Trainable Hardware Neural Networks

Herein, dual‐gate field‐effect transistors (DG FETs) fabricated on Si substrate and a corresponding NOR‐type array designed for low‐power on‐chip trainable hardware neural networks (HNNs) are presented. The fabricated DG FET exhibits notable endurance characteristics, with the subthreshold swing rem...

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Bibliographic Details
Main Authors: Kyu-Ho Lee, Dongseok Kwon, In-Seok Lee, Joon Hwang, Jiseong Im, Jong-Ho Bae, Woo Young Choi, Sung Yun Woo, Jong-Ho Lee
Format: Article
Language:English
Published: Wiley 2024-01-01
Series:Advanced Intelligent Systems
Subjects:
dual-gate field-effect transistors
gradient descent algorithms
hardware-based neural networks
NOR-type arrays
on-chip training
Online Access:https://doi.org/10.1002/aisy.202300490

Internet

https://doi.org/10.1002/aisy.202300490

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