Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications
In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, w...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2017-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8046149/ |