IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions
Abstract A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be secretly introduced into the processo...
| Autors principals: | , , |
|---|---|
| Format: | Article |
| Idioma: | English |
| Publicat: |
Wiley
2022-07-01
|
| Col·lecció: | IET Information Security |
| Matèries: | |
| Accés en línia: | https://doi.org/10.1049/ise2.12059 |