Fault-tolerant method for anti-SEU of embedded system based on dual-core processor
The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article pres...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2019-10-01
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| Series: | The Journal of Engineering |
| Subjects: | |
| Online Access: | https://digital-library.theiet.org/content/journals/10.1049/joe.2018.9099 |
| _version_ | 1818960431847309312 |
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| author | Xiuhai Cui Qi Gao Ruichao Wang Li Liu Jun Liang Yu Peng |
| author_facet | Xiuhai Cui Qi Gao Ruichao Wang Li Liu Jun Liang Yu Peng |
| author_sort | Xiuhai Cui |
| collection | DOAJ |
| description | The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification. |
| first_indexed | 2024-12-20T11:57:26Z |
| format | Article |
| id | doaj.art-ae95346d3d324d70b46ec5e35cc95d40 |
| institution | Directory Open Access Journal |
| issn | 2051-3305 |
| language | English |
| last_indexed | 2024-12-20T11:57:26Z |
| publishDate | 2019-10-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Journal of Engineering |
| spelling | doaj.art-ae95346d3d324d70b46ec5e35cc95d402022-12-21T19:41:37ZengWileyThe Journal of Engineering2051-33052019-10-0110.1049/joe.2018.9099JOE.2018.9099Fault-tolerant method for anti-SEU of embedded system based on dual-core processorXiuhai Cui0Qi Gao1Ruichao Wang2Li Liu3Jun Liang4Yu Peng5Harbin Institute of TechnologyChina Aerospace Science and Industry CorporationHarbin Institute of TechnologyChina Aerospace Science and Industry CorporationHarbin Institute of TechnologyHarbin Institute of TechnologyThe development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification.https://digital-library.theiet.org/content/journals/10.1049/joe.2018.9099error detectionradiation hardening (electronics)fault tolerant computingfield programmable gate arraysembedded systemsmicroprocessor chipssystem-on-chipredundancyfault-tolerant methodembedded systemdual-core processorarm processorsdual-core armsoc fpgadual-core mutual-checkcontrol flowtriple modular redundancytwo-level watchdogtwo-level fault-tolerance mechanismantiseu capabilityantianti method |
| spellingShingle | Xiuhai Cui Qi Gao Ruichao Wang Li Liu Jun Liang Yu Peng Fault-tolerant method for anti-SEU of embedded system based on dual-core processor The Journal of Engineering error detection radiation hardening (electronics) fault tolerant computing field programmable gate arrays embedded systems microprocessor chips system-on-chip redundancy fault-tolerant method embedded system dual-core processor arm processors dual-core arm soc fpga dual-core mutual-check control flow triple modular redundancy two-level watchdog two-level fault-tolerance mechanism antiseu capability antianti method |
| title | Fault-tolerant method for anti-SEU of embedded system based on dual-core processor |
| title_full | Fault-tolerant method for anti-SEU of embedded system based on dual-core processor |
| title_fullStr | Fault-tolerant method for anti-SEU of embedded system based on dual-core processor |
| title_full_unstemmed | Fault-tolerant method for anti-SEU of embedded system based on dual-core processor |
| title_short | Fault-tolerant method for anti-SEU of embedded system based on dual-core processor |
| title_sort | fault tolerant method for anti seu of embedded system based on dual core processor |
| topic | error detection radiation hardening (electronics) fault tolerant computing field programmable gate arrays embedded systems microprocessor chips system-on-chip redundancy fault-tolerant method embedded system dual-core processor arm processors dual-core arm soc fpga dual-core mutual-check control flow triple modular redundancy two-level watchdog two-level fault-tolerance mechanism antiseu capability antianti method |
| url | https://digital-library.theiet.org/content/journals/10.1049/joe.2018.9099 |
| work_keys_str_mv | AT xiuhaicui faulttolerantmethodforantiseuofembeddedsystembasedondualcoreprocessor AT qigao faulttolerantmethodforantiseuofembeddedsystembasedondualcoreprocessor AT ruichaowang faulttolerantmethodforantiseuofembeddedsystembasedondualcoreprocessor AT liliu faulttolerantmethodforantiseuofembeddedsystembasedondualcoreprocessor AT junliang faulttolerantmethodforantiseuofembeddedsystembasedondualcoreprocessor AT yupeng faulttolerantmethodforantiseuofembeddedsystembasedondualcoreprocessor |