Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates

Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates

In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthresh...

Full description

Bibliographic Details
Main Authors:	Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa, Toshiyuki Tsutsumi, Hanpei Koike
Format:	Article
Language:	English
Published:	MDPI AG 2015-05-01
Series:	Journal of Low Power Electronics and Applications
Subjects:	SOTB FD-SOI ultra-low voltage measurement on silicon
Online Access:	http://www.mdpi.com/2079-9268/5/2/116

Similar Items

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability
by: Masakazu Hioki, et al.
Published: (2014-07-01)

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks
by: Ba-Anh Dao, et al.
Published: (2021-01-01)

Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers
by: Guillaume Patrigeon, et al.
Published: (2019-01-01)

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V
by: Nobuyuki Sugii, et al.
Published: (2014-04-01)

A Thermally Stable Quasi-CMOS Bipolar Logic
by: Wieslaw Kuzmicz
Published: (2021-12-01)

Perspective of Buried Oxide Thickness Variation on Triple Metal-Gate (TMG) Recessed-S/D FD-SOI MOSFET
by: Anjali Priya, et al.
Published: (2018-01-01)

Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs
by: Soumajit Ghosh, et al.
Published: (2022-01-01)

Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies
by: Wieslaw Kuzmicz
Published: (2021-07-01)

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS
by: Liang-Wei Ouyang, et al.
Published: (2024-04-01)

A Fully Integrated 2:1 Self-Oscillating Switched-Capacitor DC–DC Converter in 28 nm UTBB FD-SOI
by: Matthew Turnquist, et al.
Published: (2016-09-01)

Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies
by: Zongru Li, et al.
Published: (2022-06-01)

High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS
by: Andrea Ballo, et al.
Published: (2020-09-01)

Simulation Perspectives of Sub-1V Single-Supply Z<sup>2</sup>-FET 1T-DRAM Cells for Low-Power
by: Carlos Navarro, et al.
Published: (2019-01-01)

Cryogenic Temperature Characterization of a 28-nm FD-SOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration
by: P. Galy, et al.
Published: (2018-01-01)

Optimization of Photoelectron <italic>In-Situ</italic> Sensing Device in FD-SOI
by: J. Liu, et al.
Published: (2021-01-01)

Assessment of Global Variability in UTBB MOSFETs in Subthreshold Regime
by: Sergej Makovejev, et al.
Published: (2014-07-01)

Probe-Dependent Residual Error Analysis for Accurate On-Wafer MOSFET Measurements up to 110 GHz
by: Lucas Nyssens, et al.
Published: (2023-01-01)

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature
by: Edoardo Catapano, et al.
Published: (2021-01-01)

Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors
by: Fernando Jose da Costa, et al.
Published: (2023-01-01)

Performance Optimization of FD-SOI Hall Sensors Via 3D TCAD Simulations
by: Linjie Fan, et al.
Published: (2020-05-01)

Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits
by: Chang Cai, et al.
Published: (2020-01-01)

A Perspective on SOI Symmetric Lateral Bipolar Transistors for Ultra-Low-Power Systems
by: Tak H. Ning
Published: (2016-01-01)

Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits
by: Jean-Pierre Raskin
Published: (2022-01-01)

A Complementary Ring Mixer Driven by a Single-Ended LO in 22-nm FD-SOI CMOS for <italic>K</italic> and <italic>Ka</italic>-Bands
by: Paolo Valerio Testa, et al.
Published: (2021-01-01)

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI
by: Enne Wittenhagen, et al.
Published: (2022-01-01)

A Flash Frequency Tuning Technique for SC-Based mm Wave VCOs
by: Alessandro Parisi, et al.
Published: (2022-01-01)

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements
by: Azam Seyedi, et al.
Published: (2022-01-01)

Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications
by: Andrea Boni, et al.
Published: (2023-01-01)

Transformer-Based VCO for W-Band Automotive Radar Applications
by: Andrea Cavarra, et al.
Published: (2021-02-01)

Investigation of Radiation Effects on FD-SOI Hall Sensors by TCAD Simulations
by: Linjie Fan, et al.
Published: (2020-07-01)

A Three-Dimensional DRAM Using Floating Body Capacitance Cells in an FD-SOI Process
by: Xuelian Liu, et al.
Published: (2013-12-01)

Importance des conditions de l’estime de soi auprès de quelques adolescents de Kinshasa
by: Clément TUNDANONGA LUMBAHE
Published: (2022-06-01)

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC
by: Robert Bogdan Staszewski, et al.
Published: (2022-01-01)

Evidence of Limitations of the Transconductance-to-Drain-Current Method (<i>g<sub>m</sub></i>/<i>I<sub>d</sub></i>) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors
by: Leonardo Barboni
Published: (2020-05-01)

Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic Temperatures
by: Anuj Bhardwaj, et al.
Published: (2023-01-01)

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K
by: Lucas Nyssens, et al.
Published: (2020-01-01)

Total Ionizing Dose Hardening of 45 nm FD-SOI MOSFETs Using Body-Tie Biasing
by: Xiaoqiang Liu, et al.
Published: (2019-01-01)

The advancement of silicon-on-insulator (SOI) devices and their basic properties
by: T.E. Rudenko, et al.
Published: (2020-09-01)

On the Nature of the Memory Mechanism of Gated-Thyristor Dynamic-RAM Cells
by: Ahmad Z. Badwan, et al.
Published: (2015-01-01)

Optimization of process parameter variations on leakage current in in silicon-oninsulator vertical double gate mosfet device
by: K.E. Kaharudin, et al.
Published: (2015-12-01)