An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors
Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compiler...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2019-07-01
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| Series: | Symmetry |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2073-8994/11/7/938 |