gm/Id$g_m/I_d$ Analysis of vertical nanowire III–V TFETs
Abstract Experimental data on analog performance of gate‐all‐around III‐V vertical Tunnel Field‐Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 n...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2023-09-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.12954 |
| Summary: | Abstract Experimental data on analog performance of gate‐all‐around III‐V vertical Tunnel Field‐Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current‐mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large‐signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage. |
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| ISSN: | 0013-5194 1350-911X |