Design of IP Core of Signal Generator of Pseudo-random Sequence Based on Nios II
The paper put forward a design method of IP core of signal generator of pseudo-random sequence according to Avalon bus specification of Nios II embedded system, and introduced hardware and software designs of the IP core in details. The method uses collaborative design of software and hardware of cu...
| Main Authors: | , |
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| Format: | Article |
| Language: | zho |
| Published: |
Editorial Department of Industry and Mine Automation
2011-02-01
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| Series: | Gong-kuang zidonghua |
| Subjects: | |
| Online Access: | http://www.gkzdh.cn/article/id/2449 |