A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology

A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology

Abstract Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard‐gated Quatro cel...

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Bibliographic Details
Main Authors: Sabavat Satheesh Kumar, Kumaravel Sundaram, Sanjeevikumar Padmanaban, Jens Bo Holm‐Nielsen, Frede Blaabjerg
Format: Article
Language:English
Published: Hindawi-IET 2021-09-01
Series:IET Circuits, Devices and Systems
Subjects:
CMOS logic circuits
flip‐flops
invertors
logic design
low‐power electronics
radiation hardening (electronics)
Online Access:https://doi.org/10.1049/cds2.12052

Internet

https://doi.org/10.1049/cds2.12052

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