A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology

A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology

Abstract Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard‐gated Quatro cel...

সম্পূর্ণ বিবরণ

গ্রন্থ-পঞ্জীর বিবরন
প্রধান লেখক: Sabavat Satheesh Kumar, Kumaravel Sundaram, Sanjeevikumar Padmanaban, Jens Bo Holm‐Nielsen, Frede Blaabjerg
বিন্যাস: প্রবন্ধ
ভাষা:English
প্রকাশিত: Hindawi-IET 2021-09-01
মালা:IET Circuits, Devices and Systems
বিষয়গুলি:
CMOS logic circuits
flip‐flops
invertors
logic design
low‐power electronics
radiation hardening (electronics)
অনলাইন ব্যবহার করুন:https://doi.org/10.1049/cds2.12052

আন্তর্জাল

https://doi.org/10.1049/cds2.12052

অনুরূপ উপাদানগুলি