FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring System
A field-programmable gate array (FPGA) based system for digital filtering in a neonatal heart rate monitoring system is presented. The system employs electric potential sensors (EPS) and contains a single hardware filter stage for antialiasing. The remaining digital signal processing required to pro...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-11-01
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| Series: | Engineering Proceedings |
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| Online Access: | https://www.mdpi.com/2673-4591/27/1/70 |
| _version_ | 1797611997126197248 |
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| author | Henry Dore Rodrigo Aviles-Espinosa Elizabeth Rendon-Morales |
| author_facet | Henry Dore Rodrigo Aviles-Espinosa Elizabeth Rendon-Morales |
| author_sort | Henry Dore |
| collection | DOAJ |
| description | A field-programmable gate array (FPGA) based system for digital filtering in a neonatal heart rate monitoring system is presented. The system employs electric potential sensors (EPS) and contains a single hardware filter stage for antialiasing. The remaining digital signal processing required to provide a clinical standard electrocardiogram (ECG) is performed on the FPGA (myRIO 1900, National Instruments Corporation of Austin, Austin, TX, USA). This is compared with a previous microprocessor version (Raspberry Pi 3, BCM2837 processor, Raspberry Pi Ltd, Cambridge, UK) containing a dual hardware/software filtering scheme, with the aim of simplifying the analog front end and allowing for reconfigurable filtering in the digital domain. A custom neonate phantom was employed to emulate real world conditions and ambient noise. The developed FPGA system was shown to have a signal quality comparable with the microprocessor implementation, with an average signal-to-noise ratio loss of 2%. A 12 dB increase in the attenuation of the predominant 50 Hz noise was shown, indicating filter effectiveness gains. The phantom was used to broadcast data from the preterm infant cardio-respiratory signals database (PICSDB) and the FPGA filtering scheme was shown to remove the majority of the ambient 50 Hz noise with an average reduction of 30 dB, and provided a clean ECG signal. These results demonstrate that FPGA-filtered EPS ECGs have comparable signal quality to the combined HW/SW filtering implementation, with a reduction in complexity and power consumption. |
| first_indexed | 2024-03-11T06:36:11Z |
| format | Article |
| id | doaj.art-b39d316809eb498d9e6b759bc5e2216c |
| institution | Directory Open Access Journal |
| issn | 2673-4591 |
| language | English |
| last_indexed | 2024-03-11T06:36:11Z |
| publishDate | 2022-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Engineering Proceedings |
| spelling | doaj.art-b39d316809eb498d9e6b759bc5e2216c2023-11-17T10:55:17ZengMDPI AGEngineering Proceedings2673-45912022-11-012717010.3390/ecsa-9-13258FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring SystemHenry Dore0Rodrigo Aviles-Espinosa1Elizabeth Rendon-Morales2Robotics and Mechatronics Systems Research Group, School of Engineering and Informatics, University of Sussex, Falmer BN1 9RH, UKRobotics and Mechatronics Systems Research Group, School of Engineering and Informatics, University of Sussex, Falmer BN1 9RH, UKRobotics and Mechatronics Systems Research Group, School of Engineering and Informatics, University of Sussex, Falmer BN1 9RH, UKA field-programmable gate array (FPGA) based system for digital filtering in a neonatal heart rate monitoring system is presented. The system employs electric potential sensors (EPS) and contains a single hardware filter stage for antialiasing. The remaining digital signal processing required to provide a clinical standard electrocardiogram (ECG) is performed on the FPGA (myRIO 1900, National Instruments Corporation of Austin, Austin, TX, USA). This is compared with a previous microprocessor version (Raspberry Pi 3, BCM2837 processor, Raspberry Pi Ltd, Cambridge, UK) containing a dual hardware/software filtering scheme, with the aim of simplifying the analog front end and allowing for reconfigurable filtering in the digital domain. A custom neonate phantom was employed to emulate real world conditions and ambient noise. The developed FPGA system was shown to have a signal quality comparable with the microprocessor implementation, with an average signal-to-noise ratio loss of 2%. A 12 dB increase in the attenuation of the predominant 50 Hz noise was shown, indicating filter effectiveness gains. The phantom was used to broadcast data from the preterm infant cardio-respiratory signals database (PICSDB) and the FPGA filtering scheme was shown to remove the majority of the ambient 50 Hz noise with an average reduction of 30 dB, and provided a clean ECG signal. These results demonstrate that FPGA-filtered EPS ECGs have comparable signal quality to the combined HW/SW filtering implementation, with a reduction in complexity and power consumption.https://www.mdpi.com/2673-4591/27/1/70heart rateFPGAECGnewbornmedical devicesDSP |
| spellingShingle | Henry Dore Rodrigo Aviles-Espinosa Elizabeth Rendon-Morales FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring System Engineering Proceedings heart rate FPGA ECG newborn medical devices DSP |
| title | FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring System |
| title_full | FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring System |
| title_fullStr | FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring System |
| title_full_unstemmed | FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring System |
| title_short | FPGA Implementation of ECG Signal Processing for Use in a Neonatal Heart Rate Monitoring System |
| title_sort | fpga implementation of ecg signal processing for use in a neonatal heart rate monitoring system |
| topic | heart rate FPGA ECG newborn medical devices DSP |
| url | https://www.mdpi.com/2673-4591/27/1/70 |
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