Test environment for verification of multi-processor memory subsystem unit
State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency. An implementation of memory subsystem in HDL (hardware description language) is complex and error-prone task. Ensuring the correct functioning of...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Ivannikov Institute for System Programming of the Russian Academy of Sciences
2019-09-01
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| Series: | Труды Института системного программирования РАН |
| Subjects: | |
| Online Access: | https://ispranproceedings.elpub.ru/jour/article/view/1180 |