Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology
The design of a full adder involves the use of logic gates so that the design can convert 8 inputs to create a byte-wide adder and to force the carry bit to the other adder. However, the uses of multiplexers to replace the logic gates in the construction of the full adder is proven to be possible...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Penteract Technology
2023-02-01
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| Series: | Malaysian Journal of Science and Advanced Technology |
| Subjects: | |
| Online Access: | https://mjsat.com.my/index.php/mjsat/article/view/59 |