Improving Hardware in LUT-Based Mealy FSMs

Improving Hardware in LUT-Based Mealy FSMs

The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables an...

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Bibliographic Details
Main Authors: Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki
Format: Article
Language:English
Published: MDPI AG 2022-08-01
Series:Applied Sciences
Subjects:
Mealy FSM
FPGA
LUT count
synthesis
collection of outputs
Online Access:https://www.mdpi.com/2076-3417/12/16/8065

Internet

https://www.mdpi.com/2076-3417/12/16/8065

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