Improving Hardware in LUT-Based Mealy FSMs
The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables an...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-08-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/12/16/8065 |
| _version_ | 1797411378865111040 |
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| author | Alexander Barkalov Larysa Titarenko Kazimierz Krzywicki |
| author_facet | Alexander Barkalov Larysa Titarenko Kazimierz Krzywicki |
| author_sort | Alexander Barkalov |
| collection | DOAJ |
| description | The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs. |
| first_indexed | 2024-03-09T04:45:16Z |
| format | Article |
| id | doaj.art-b4edec2ef5484df2a2faf21ca2420b55 |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-09T04:45:16Z |
| publishDate | 2022-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-b4edec2ef5484df2a2faf21ca2420b552023-12-03T13:17:04ZengMDPI AGApplied Sciences2076-34172022-08-011216806510.3390/app12168065Improving Hardware in LUT-Based Mealy FSMsAlexander Barkalov0Larysa Titarenko1Kazimierz Krzywicki2Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, Ul. Licealna 9, 65-417 Zielona Gora, PolandInstitute of Metrology, Electronics and Computer Science, University of Zielona Gora, Ul. Licealna 9, 65-417 Zielona Gora, PolandDepartment of Technology, The Jacob of Paradies University, Ul. Teatralna 25, 66-400 Gorzow Wielkopolski, PolandThe main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs.https://www.mdpi.com/2076-3417/12/16/8065Mealy FSMFPGALUT countsynthesiscollection of outputs |
| spellingShingle | Alexander Barkalov Larysa Titarenko Kazimierz Krzywicki Improving Hardware in LUT-Based Mealy FSMs Applied Sciences Mealy FSM FPGA LUT count synthesis collection of outputs |
| title | Improving Hardware in LUT-Based Mealy FSMs |
| title_full | Improving Hardware in LUT-Based Mealy FSMs |
| title_fullStr | Improving Hardware in LUT-Based Mealy FSMs |
| title_full_unstemmed | Improving Hardware in LUT-Based Mealy FSMs |
| title_short | Improving Hardware in LUT-Based Mealy FSMs |
| title_sort | improving hardware in lut based mealy fsms |
| topic | Mealy FSM FPGA LUT count synthesis collection of outputs |
| url | https://www.mdpi.com/2076-3417/12/16/8065 |
| work_keys_str_mv | AT alexanderbarkalov improvinghardwareinlutbasedmealyfsms AT larysatitarenko improvinghardwareinlutbasedmealyfsms AT kazimierzkrzywicki improvinghardwareinlutbasedmealyfsms |