| Summary: | Nanotube (NT) FETs have been proposed as the most promising architecture for the ultimate scaling of FETs. However, an enhanced L-BTBT restricts their scaling. Therefore, in this paper, for the first time, we explore the application of a dual-material gate (DMG) in the emerging NT junctionless accumulation mode FETs and NT metal-oxide semiconductor FETs to alleviate the detrimental BTBT. The incorporation of DMG reduces the OFF-state current in the NTFETs by more than two orders of magnitude leading to a substantial ON-state to OFF-state current ratio (ION/IOFF) of ~106 for a gate length of 20 nm. This paper shows that the DMG architecture not only improves the static performance significantly but also leads to an enhanced dynamic performance due to a reduction in the total gate capacitance. In addition, we also provide the essential design guidelines for NTFETs in terms of the work function of the dual gates and their respective lengths. Since the NT architecture is essentially vertical, the DMG can be realized by the deposition processes facilitating the scaling of the DMG NTFETs unlike the lateral DMG FETs. Therefore, this paper provides an incentive for experimentally exploring the NTFETs for the future technology nodes.
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