A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and...

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Bibliographic Details
Main Authors: Fang Tang, Qiyun Ma, Zhou Shu, Yuanjin Zheng, Amine Bermak
Format: Article
Language:English
Published: MDPI AG 2021-11-01
Series:Electronics
Subjects:
SAR
ADC
high linearity
low power
switching procedure
Online Access:https://www.mdpi.com/2079-9292/10/22/2856

Internet

https://www.mdpi.com/2079-9292/10/22/2856

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