On Verification of PLC-Programs Written in the LD-Language

On Verification of PLC-Programs Written in the LD-Language

Show other versions (1)

We discuss some questions connected with the construction of a technology of analysing correctness of Programmable Logic Controller programs. We consider an example of modeling and automated verification of PLC-programs written in the Ladder Diagram language (including timed function blocks) of the...

Full description

Bibliographic Details
Main Authors: E. V. Kuzmin, V. A. Sokolov
Format: Article
Language:English
Published: Yaroslavl State University 2015-02-01
Series:Моделирование и анализ информационных систем
Subjects:
верификация
проверка модели
программы логических контроллеров
ld-диаграммы
Online Access:https://www.mais-journal.ru/jour/article/view/24

Internet

https://www.mais-journal.ru/jour/article/view/24

Similar Items