A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretica...

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Bibliographic Details
Main Authors: Chenggang Yan, Chen Hu, Jianhui Wu
Format: Article
Language:English
Published: MDPI AG 2019-07-01
Series:Applied Sciences
Subjects:
digital-to-time converter (DTC)
three delay lines Vernier principle
field programmable gate arrays (FPGA), phase lock loop (PLL)
Online Access:https://www.mdpi.com/2076-3417/9/13/2705

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https://www.mdpi.com/2076-3417/9/13/2705

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