A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretica...
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| Format: | Article |
| Language: | English |
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MDPI AG
2019-07-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/9/13/2705 |
| _version_ | 1830417311678332928 |
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| author | Chenggang Yan Chen Hu Jianhui Wu |
| author_facet | Chenggang Yan Chen Hu Jianhui Wu |
| author_sort | Chenggang Yan |
| collection | DOAJ |
| description | In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretical fine resolution of the proposed DTC is improved by calculating the period difference two times. The achieved resolution of the proposed DTC is 203 fs realized with an Altera Stratix III FPGA chip, which is about tenfold higher than traditional FPGA-DTC implemented with the same series FPGAs. The worst absolute differential nonlinearity (DNL) and integral nonlinearity (INL) are verified smaller than 0.88 least significant bit (LSB) and 4.4 LSB, respectively. By optimized computation logic, there are only 448 adaptive look-up-tables (ALUTs), 237 registers and three phase locked loops (PLLs) utilized for circuit implementation. Experimental results prove that the proposed DTC features high resolution with low cost. |
| first_indexed | 2024-12-20T21:39:34Z |
| format | Article |
| id | doaj.art-ba92bb50cd7c47e4ba2831db84530b55 |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-12-20T21:39:34Z |
| publishDate | 2019-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-ba92bb50cd7c47e4ba2831db84530b552022-12-21T19:25:51ZengMDPI AGApplied Sciences2076-34172019-07-01913270510.3390/app9132705app9132705A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGAChenggang Yan0Chen Hu1Jianhui Wu2National ASIC system engineering research center, Southeast University, Nanjing 210096, ChinaNational ASIC system engineering research center, Southeast University, Nanjing 210096, ChinaNational ASIC system engineering research center, Southeast University, Nanjing 210096, ChinaIn this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretical fine resolution of the proposed DTC is improved by calculating the period difference two times. The achieved resolution of the proposed DTC is 203 fs realized with an Altera Stratix III FPGA chip, which is about tenfold higher than traditional FPGA-DTC implemented with the same series FPGAs. The worst absolute differential nonlinearity (DNL) and integral nonlinearity (INL) are verified smaller than 0.88 least significant bit (LSB) and 4.4 LSB, respectively. By optimized computation logic, there are only 448 adaptive look-up-tables (ALUTs), 237 registers and three phase locked loops (PLLs) utilized for circuit implementation. Experimental results prove that the proposed DTC features high resolution with low cost.https://www.mdpi.com/2076-3417/9/13/2705digital-to-time converter (DTC)three delay lines Vernier principlefield programmable gate arrays (FPGA), phase lock loop (PLL) |
| spellingShingle | Chenggang Yan Chen Hu Jianhui Wu A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA Applied Sciences digital-to-time converter (DTC) three delay lines Vernier principle field programmable gate arrays (FPGA), phase lock loop (PLL) |
| title | A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA |
| title_full | A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA |
| title_fullStr | A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA |
| title_full_unstemmed | A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA |
| title_short | A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA |
| title_sort | high resolution vernier digital to time converter implemented with 65 nm fpga |
| topic | digital-to-time converter (DTC) three delay lines Vernier principle field programmable gate arrays (FPGA), phase lock loop (PLL) |
| url | https://www.mdpi.com/2076-3417/9/13/2705 |
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