Hardware Implementation of High-Throughput S-Box in AES for Information Security

Hardware Implementation of High-Throughput S-Box in AES for Information Security

The Advanced Encryption Standard (AES) is used for achieving quantum-resistant cryptography when a 256-bit key is applied. This paper presents a high-throughput, seven-stage hardware pipeline architecture for SubByte computations in the AES for information security applications. Composite field arit...

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Bibliographic Details
Main Authors: Shih-Hsiang Lin, Jun-Yi Lee, Chia-Chou Chuang, Narn-Yih Lee, Pei-Yin Chen, Wen-Long Chin
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
AES
hardware
high-throughput
information security
S-box
Online Access:https://ieeexplore.ieee.org/document/10146260/

Internet

https://ieeexplore.ieee.org/document/10146260/

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