Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etchi...

Full description

Bibliographic Details
Main Authors: Yinhua Cui, Jeong Yeul Jeong, Yuan Gao, Sung Gyu Pyo
Format: Article
Language:English
Published: MDPI AG 2019-12-01
Series:Micromachines
Subjects:
multilevel metallization
logic device
rf etching
Online Access:https://www.mdpi.com/2072-666X/11/1/32

Internet

https://www.mdpi.com/2072-666X/11/1/32

Similar Items