Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices
This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etchi...
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| Format: | Article |
| Language: | English |
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MDPI AG
2019-12-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/11/1/32 |
| _version_ | 1818536604855173120 |
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| author | Yinhua Cui Jeong Yeul Jeong Yuan Gao Sung Gyu Pyo |
| author_facet | Yinhua Cui Jeong Yeul Jeong Yuan Gao Sung Gyu Pyo |
| author_sort | Yinhua Cui |
| collection | DOAJ |
| description | This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etching 200 Å IMP Ti (ion metal plasma titanium) 200 Å CVD TiN (titanium nitride deposited by chemical vapor deposition) 2 × 50 Å. The resistivities of the glue layer and barrier, i.e., IMP Ti and CVD TiN, were 73 and 280 μΩ·cm, respectively, and the bottom coverages were 57% and 80%, respectively, at a 3.2:1 aspect ratio (A/R). The specific resistance of the tungsten film was approximately 11.5 μΩ·cm, and it was confirmed that the via filling could be performed smoothly. RF etching and IMP Ti should be at least 200 Å each, and CVD TiN can be performed satisfactorily with the existing 2 × 50 Å process. Tungsten deposition showed no difference in the via resistance with deposition temperature and SiH<sub>4</sub> reduction time. When the barrier scheme of RF etching 200 Å IMP Ti 200 ÅCVD TiN 2 × 50 Å was applied, the via resistance was less than 20 Ω, even with a side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm. |
| first_indexed | 2024-12-11T18:40:06Z |
| format | Article |
| id | doaj.art-bbde604304344cec96c491477ffb55f9 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-12-11T18:40:06Z |
| publishDate | 2019-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-bbde604304344cec96c491477ffb55f92022-12-22T00:54:39ZengMDPI AGMicromachines2072-666X2019-12-011113210.3390/mi11010032mi11010032Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic DevicesYinhua Cui0Jeong Yeul Jeong1Yuan Gao2Sung Gyu Pyo3School of Integrative Engineering, Chung-Ang University, Seoul 06974, KoreaProcess Development Center, Magnachip Semiconductor, Seoul 15213, KoreaSchool of Integrative Engineering, Chung-Ang University, Seoul 06974, KoreaSchool of Integrative Engineering, Chung-Ang University, Seoul 06974, KoreaThis paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etching 200 Å IMP Ti (ion metal plasma titanium) 200 Å CVD TiN (titanium nitride deposited by chemical vapor deposition) 2 × 50 Å. The resistivities of the glue layer and barrier, i.e., IMP Ti and CVD TiN, were 73 and 280 μΩ·cm, respectively, and the bottom coverages were 57% and 80%, respectively, at a 3.2:1 aspect ratio (A/R). The specific resistance of the tungsten film was approximately 11.5 μΩ·cm, and it was confirmed that the via filling could be performed smoothly. RF etching and IMP Ti should be at least 200 Å each, and CVD TiN can be performed satisfactorily with the existing 2 × 50 Å process. Tungsten deposition showed no difference in the via resistance with deposition temperature and SiH<sub>4</sub> reduction time. When the barrier scheme of RF etching 200 Å IMP Ti 200 ÅCVD TiN 2 × 50 Å was applied, the via resistance was less than 20 Ω, even with a side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm.https://www.mdpi.com/2072-666X/11/1/32multilevel metallizationlogic devicerf etching |
| spellingShingle | Yinhua Cui Jeong Yeul Jeong Yuan Gao Sung Gyu Pyo Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices Micromachines multilevel metallization logic device rf etching |
| title | Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices |
| title_full | Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices |
| title_fullStr | Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices |
| title_full_unstemmed | Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices |
| title_short | Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices |
| title_sort | process optimization of via plug multilevel interconnections in cmos logic devices |
| topic | multilevel metallization logic device rf etching |
| url | https://www.mdpi.com/2072-666X/11/1/32 |
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