A BIST Scheme for Dynamic Comparators
This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The pro...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-12-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/24/4169 |
| _version_ | 1797460069280907264 |
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| author | Xiao-Bin Tang Masayoshi Tachibana |
| author_facet | Xiao-Bin Tang Masayoshi Tachibana |
| author_sort | Xiao-Bin Tang |
| collection | DOAJ |
| description | This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results. |
| first_indexed | 2024-03-09T16:59:41Z |
| format | Article |
| id | doaj.art-bc07be6bb48a40b4926dc0892686359b |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T16:59:41Z |
| publishDate | 2022-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-bc07be6bb48a40b4926dc0892686359b2023-11-24T14:31:30ZengMDPI AGElectronics2079-92922022-12-011124416910.3390/electronics11244169A BIST Scheme for Dynamic ComparatorsXiao-Bin Tang0Masayoshi Tachibana1Electronic and Photonic Systems Engineering Course, Department of Engineering, Graduate School of Enginering, Kochi University of Technology, 185 Miyanokuchi, Tosayamada, Kami, Kochi 782-8502, JapanElectronic and Photonic Systems Engineering Course, Department of Engineering, Graduate School of Enginering, Kochi University of Technology, 185 Miyanokuchi, Tosayamada, Kami, Kochi 782-8502, JapanThis paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results.https://www.mdpi.com/2079-9292/11/24/4169built-in self-testfault diagnosisdynamic comparator |
| spellingShingle | Xiao-Bin Tang Masayoshi Tachibana A BIST Scheme for Dynamic Comparators Electronics built-in self-test fault diagnosis dynamic comparator |
| title | A BIST Scheme for Dynamic Comparators |
| title_full | A BIST Scheme for Dynamic Comparators |
| title_fullStr | A BIST Scheme for Dynamic Comparators |
| title_full_unstemmed | A BIST Scheme for Dynamic Comparators |
| title_short | A BIST Scheme for Dynamic Comparators |
| title_sort | bist scheme for dynamic comparators |
| topic | built-in self-test fault diagnosis dynamic comparator |
| url | https://www.mdpi.com/2079-9292/11/24/4169 |
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