Simulator Semantics for System Level Formal Verification
Many simulation based Bounded Model Checking approaches to System Level Formal Verification (SLFV) have been devised. Typically such approaches exploit the capability of simulators to save computation time by saving and restoring the state of the system under simulation. However, even though such ap...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Open Publishing Association
2015-09-01
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| Series: | Electronic Proceedings in Theoretical Computer Science |
| Online Access: | http://arxiv.org/pdf/1509.07201v1 |