A low latency and low power indirect topology for on-chip communication.
This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Bu...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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Public Library of Science (PLoS)
2019-01-01
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| Series: | PLoS ONE |
| Online Access: | https://doi.org/10.1371/journal.pone.0222759 |
| _version_ | 1818584119937859584 |
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| author | Usman Ali Gulzari Sarzamin Khan Muhammad Sajid Sheraz Anjum Frank Sill Torres Hessam Sarjoughian Abdullah Gani |
| author_facet | Usman Ali Gulzari Sarzamin Khan Muhammad Sajid Sheraz Anjum Frank Sill Torres Hessam Sarjoughian Abdullah Gani |
| author_sort | Usman Ali Gulzari |
| collection | DOAJ |
| description | This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively. |
| first_indexed | 2024-12-16T08:16:07Z |
| format | Article |
| id | doaj.art-bd5483e2ce924b95b1dea00525f9420c |
| institution | Directory Open Access Journal |
| issn | 1932-6203 |
| language | English |
| last_indexed | 2024-12-16T08:16:07Z |
| publishDate | 2019-01-01 |
| publisher | Public Library of Science (PLoS) |
| record_format | Article |
| series | PLoS ONE |
| spelling | doaj.art-bd5483e2ce924b95b1dea00525f9420c2022-12-21T22:38:15ZengPublic Library of Science (PLoS)PLoS ONE1932-62032019-01-011410e022275910.1371/journal.pone.0222759A low latency and low power indirect topology for on-chip communication.Usman Ali GulzariSarzamin KhanMuhammad SajidSheraz AnjumFrank Sill TorresHessam SarjoughianAbdullah GaniThis paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.https://doi.org/10.1371/journal.pone.0222759 |
| spellingShingle | Usman Ali Gulzari Sarzamin Khan Muhammad Sajid Sheraz Anjum Frank Sill Torres Hessam Sarjoughian Abdullah Gani A low latency and low power indirect topology for on-chip communication. PLoS ONE |
| title | A low latency and low power indirect topology for on-chip communication. |
| title_full | A low latency and low power indirect topology for on-chip communication. |
| title_fullStr | A low latency and low power indirect topology for on-chip communication. |
| title_full_unstemmed | A low latency and low power indirect topology for on-chip communication. |
| title_short | A low latency and low power indirect topology for on-chip communication. |
| title_sort | low latency and low power indirect topology for on chip communication |
| url | https://doi.org/10.1371/journal.pone.0222759 |
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