Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...
| मुख्य लेखकों: | , , |
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| स्वरूप: | लेख |
| भाषा: | English |
| प्रकाशित: |
Wiley
2008-01-01
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| श्रृंखला: | International Journal of Reconfigurable Computing |
| ऑनलाइन पहुंच: | http://dx.doi.org/10.1155/2008/674340 |
| _version_ | 1826837182407507968 |
|---|---|
| author | Johan Ditmar Steve McKeever Alex Wilson |
| author_facet | Johan Ditmar Steve McKeever Alex Wilson |
| author_sort | Johan Ditmar |
| collection | DOAJ |
| description | This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when
targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus
allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation
details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the
function. The second is a novel algorithm for mapping arrays to memories which involves assigning array
accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm
assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem
more efficiently for a wider range of memories compared to existing methods. Both optimisations operate
on a high-level program representation and have been implemented in a commercial SystemC compiler.
Experiments show that in suitable circumstances these techniques result in significant reductions in logic
utilisation for FPGAs. |
| first_indexed | 2024-04-12T23:08:21Z |
| format | Article |
| id | doaj.art-bdc115cbaac84d99bee82e43e34dd640 |
| institution | Directory Open Access Journal |
| issn | 1687-7195 1687-7209 |
| language | English |
| last_indexed | 2025-02-16T11:38:41Z |
| publishDate | 2008-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj.art-bdc115cbaac84d99bee82e43e34dd6402025-02-03T01:07:43ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092008-01-01200810.1155/2008/674340674340Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware CompilationJohan Ditmar0Steve McKeever1Alex Wilson2Kellogg College, University of Oxford, 62 Banbury Road, Oxford OX2 6PN, UKOxford University Computing Laboratory, Wolfson Building, Parks Road, Oxford OX1 3QD, UKCeloxica Ltd., 66 Milton Park, Abingdon, Oxfordshire OX14 4RX, UKThis paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.http://dx.doi.org/10.1155/2008/674340 |
| spellingShingle | Johan Ditmar Steve McKeever Alex Wilson Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation International Journal of Reconfigurable Computing |
| title | Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation |
| title_full | Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation |
| title_fullStr | Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation |
| title_full_unstemmed | Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation |
| title_short | Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation |
| title_sort | area optimisation for field programmable gate arrays in systemc hardware compilation |
| url | http://dx.doi.org/10.1155/2008/674340 |
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