Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2008-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2008/674340 |