Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter u...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi-IET
2021-01-01
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| Series: | IET Computers & Digital Techniques |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cdt2.12002 |