A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers
A high-speed serial interface is the core IP of a high-performance computer, data center and interconnection network; its bandwidth and bit error performance restrict the development of the system. With the evolution of high-speed serial interface line rates from 56 G to 112 G in high-end informatio...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2022-09-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/11/18/2906 |