Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning

Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning

Accurate current-voltage (I-V) modeling based on the Berkeley short-channel insulated-gate field-effect transistor model (BSIM) is pivotal for integrated circuit simulation. However, the current BSIM model does not support a buried-channel-array transistor (BCAT), which is the structure of the state...

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Bibliographic Details
Main Authors: Jun Hui Park, Jung Nam Kim, Seonhaeng Lee, Gang-Jun Kim, Namhyun Lee, Rock-Hyun Baek, Dae Hwan Kim, Changhyun Kim, Myounggon Kang, Yoon Kim
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
BSIM-CMG
deep learning
genetic algorithm
I-V modeling
compact modeling
BCAT
Online Access:https://ieeexplore.ieee.org/document/10411873/

Internet

https://ieeexplore.ieee.org/document/10411873/

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