A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch be...

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Bibliographic Details
Main Authors: Cheng Wang, Zhanpeng Yang, Xinpeng Xing, Quanzhen Duan, Xinfa Zheng, Georges Gielen
Format: Article
Language:English
Published: MDPI AG 2023-09-01
Series:Electronics
Subjects:
comparator multiplexing
SAR ADC
offset mismatch
time interleaved
split CDAC
clock decoupling
Online Access:https://www.mdpi.com/2079-9292/12/19/4062

Internet

https://www.mdpi.com/2079-9292/12/19/4062

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