A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing
This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch be...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/19/4062 |
| _version_ | 1797575996171354112 |
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| author | Cheng Wang Zhanpeng Yang Xinpeng Xing Quanzhen Duan Xinfa Zheng Georges Gielen |
| author_facet | Cheng Wang Zhanpeng Yang Xinpeng Xing Quanzhen Duan Xinfa Zheng Georges Gielen |
| author_sort | Cheng Wang |
| collection | DOAJ |
| description | This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works. |
| first_indexed | 2024-03-10T21:46:59Z |
| format | Article |
| id | doaj.art-bfea5ce3cbe248d3afdb0bc5365eb4a5 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T21:46:59Z |
| publishDate | 2023-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-bfea5ce3cbe248d3afdb0bc5365eb4a52023-11-19T14:16:41ZengMDPI AGElectronics2079-92922023-09-011219406210.3390/electronics12194062A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator MultiplexingCheng Wang0Zhanpeng Yang1Xinpeng Xing2Quanzhen Duan3Xinfa Zheng4Georges Gielen5Shenzhen International Graduate School, Tsinghua University, Shenzhen 518057, ChinaShenzhen International Graduate School, Tsinghua University, Shenzhen 518057, ChinaSchool of Integrated Circuits, Sun Yat-sen University, Shenzhen 518107, ChinaSchool of Integrated Circuits, Sun Yat-sen University, Shenzhen 518107, ChinaDepartment of Elektrotechniek, ESAT-MICAS, KU Leuven, B-3001 Leuven, BelgiumDepartment of Elektrotechniek, ESAT-MICAS, KU Leuven, B-3001 Leuven, BelgiumThis paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.https://www.mdpi.com/2079-9292/12/19/4062comparator multiplexingSAR ADCoffset mismatchtime interleavedsplit CDACclock decoupling |
| spellingShingle | Cheng Wang Zhanpeng Yang Xinpeng Xing Quanzhen Duan Xinfa Zheng Georges Gielen A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing Electronics comparator multiplexing SAR ADC offset mismatch time interleaved split CDAC clock decoupling |
| title | A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing |
| title_full | A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing |
| title_fullStr | A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing |
| title_full_unstemmed | A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing |
| title_short | A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing |
| title_sort | 10 bit 400 ms s dual channel time interleaved sar adc based on comparator multiplexing |
| topic | comparator multiplexing SAR ADC offset mismatch time interleaved split CDAC clock decoupling |
| url | https://www.mdpi.com/2079-9292/12/19/4062 |
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