CCSDS 131.2-B-1 Serial Concatenated Convolutional Turbo Decoder Architecture for Efficient FPGA Implementation

CCSDS 131.2-B-1 Serial Concatenated Convolutional Turbo Decoder Architecture for Efficient FPGA Implementation

Most of the turbo encoding schemes at standards are parallel-based, so different architectures for efficient implementation are common in the literature. However, a serial turbo decoder is not that common. This scheme is used in CCSDS 131.2-B-1 standard, which is attracting much of attention recentl...

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Bibliographic Details
Main Authors: Miguel Angel Perez Naranjo, Victor P. Gil Jimenez
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
DSP
coding
FEC
serial turbodecoder
pipeline
convolutional
Online Access:https://ieeexplore.ieee.org/document/10013673/

Internet

https://ieeexplore.ieee.org/document/10013673/

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