REDUCING LDPC DECODER COMPLEXITY BY USING FPGA BASED ON MIN SUM ALGORITHM
Low-Density Parity-Check (LDPC) code approaches Shannon–limit execution for twofold field and long code lengths. The point of this work is to propose an LDPC calculation for Min Sum (MS) deciphering and playing out its equipment execution investigation inside a proposed communication framework. T...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Faculty of Engineering, University of Kufa
2022-01-01
|
| Series: | Mağallaẗ Al-kūfaẗ Al-handasiyyaẗ |
| Subjects: | |
| Online Access: | https://journal.uokufa.edu.iq/index.php/kje/article/view/1673 |