A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors
In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2021-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9355405/ |