A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors
In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9355405/ |
| _version_ | 1819120531484442624 |
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| author | Kumari Neeraj Kaushal Nihar R. Mohapatra |
| author_facet | Kumari Neeraj Kaushal Nihar R. Mohapatra |
| author_sort | Kumari Neeraj Kaushal |
| collection | DOAJ |
| description | In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves the drive capability (upto ~30%), analog FoMs and hot-carrier reliability of LDMOS transistors without any penalty on the OFF-state performance. The performance improvement is independent of drift region design (breakdown voltage). The device physics behind different observations is also discussed with detailed TCAD simulations. |
| first_indexed | 2024-12-22T06:22:09Z |
| format | Article |
| id | doaj.art-c233f3cd35504a61ab1c33fb636cfff1 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-22T06:22:09Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-c233f3cd35504a61ab1c33fb636cfff12022-12-21T18:35:55ZengIEEEIEEE Journal of the Electron Devices Society2168-67342021-01-01933434110.1109/JEDS.2021.30598549355405A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS TransistorsKumari Neeraj Kaushal0https://orcid.org/0000-0002-1369-2603Nihar R. Mohapatra1https://orcid.org/0000-0002-8827-5417Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, IndiaIn this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves the drive capability (upto ~30%), analog FoMs and hot-carrier reliability of LDMOS transistors without any penalty on the OFF-state performance. The performance improvement is independent of drift region design (breakdown voltage). The device physics behind different observations is also discussed with detailed TCAD simulations.https://ieeexplore.ieee.org/document/9355405/PMICLDMOSdoping gradientbreakdown voltagespecific on-resistancetrans-conductance |
| spellingShingle | Kumari Neeraj Kaushal Nihar R. Mohapatra A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors IEEE Journal of the Electron Devices Society PMIC LDMOS doping gradient breakdown voltage specific on-resistance trans-conductance |
| title | A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors |
| title_full | A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors |
| title_fullStr | A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors |
| title_full_unstemmed | A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors |
| title_short | A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors |
| title_sort | zero cost technique to improve on state performance and reliability of power ldmos transistors |
| topic | PMIC LDMOS doping gradient breakdown voltage specific on-resistance trans-conductance |
| url | https://ieeexplore.ieee.org/document/9355405/ |
| work_keys_str_mv | AT kumarineerajkaushal azerocosttechniquetoimproveonstateperformanceandreliabilityofpowerldmostransistors AT niharrmohapatra azerocosttechniquetoimproveonstateperformanceandreliabilityofpowerldmostransistors AT kumarineerajkaushal zerocosttechniquetoimproveonstateperformanceandreliabilityofpowerldmostransistors AT niharrmohapatra zerocosttechniquetoimproveonstateperformanceandreliabilityofpowerldmostransistors |