The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology
To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S<sup>2</sup>P) converter for 5G applications based on th...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2021-01-01
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| Series: | Applied Sciences |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2076-3417/11/1/429 |
| Summary: | To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S<sup>2</sup>P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S<sup>2</sup>P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm<sup>2</sup> and operates successfully over a wide clock frequency range from 5 M to 40 MHz. |
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| ISSN: | 2076-3417 |