The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology
To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S<sup>2</sup>P) converter for 5G applications based on th...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-01-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/11/1/429 |
| _version_ | 1797542427555266560 |
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| author | Min-Su Kim Youngoo Yang Hyungmo Koo Hansik Oh |
| author_facet | Min-Su Kim Youngoo Yang Hyungmo Koo Hansik Oh |
| author_sort | Min-Su Kim |
| collection | DOAJ |
| description | To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S<sup>2</sup>P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S<sup>2</sup>P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm<sup>2</sup> and operates successfully over a wide clock frequency range from 5 M to 40 MHz. |
| first_indexed | 2024-03-10T13:30:20Z |
| format | Article |
| id | doaj.art-c44f20e4ba2b4f098e43d1cb41fcaf22 |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-10T13:30:20Z |
| publishDate | 2021-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-c44f20e4ba2b4f098e43d1cb41fcaf222023-11-21T08:08:40ZengMDPI AGApplied Sciences2076-34172021-01-0111142910.3390/app11010429The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS TechnologyMin-Su Kim0Youngoo Yang1Hyungmo Koo2Hansik Oh3Department of Digital Electronics, Dealim University College, 29 Imgok-ro, Dongan-gu, Anyang-si, Gyeonggi-do 13916, KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, 2066 Seobu-ro, Jangan-gu, Suwon, Gyeonggi-do 16419, KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, 2066 Seobu-ro, Jangan-gu, Suwon, Gyeonggi-do 16419, KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, 2066 Seobu-ro, Jangan-gu, Suwon, Gyeonggi-do 16419, KoreaTo improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S<sup>2</sup>P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S<sup>2</sup>P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm<sup>2</sup> and operates successfully over a wide clock frequency range from 5 M to 40 MHz.https://www.mdpi.com/2076-3417/11/1/429serial to parallel converterdigital controllerembedded systemembedded hardware system5GRF Front-End |
| spellingShingle | Min-Su Kim Youngoo Yang Hyungmo Koo Hansik Oh The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology Applied Sciences serial to parallel converter digital controller embedded system embedded hardware system 5G RF Front-End |
| title | The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology |
| title_full | The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology |
| title_fullStr | The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology |
| title_full_unstemmed | The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology |
| title_short | The Demonstration of S<sup>2</sup>P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology |
| title_sort | demonstration of s sup 2 sup p serial to parallel converter with address allocation method using 28 nm cmos technology |
| topic | serial to parallel converter digital controller embedded system embedded hardware system 5G RF Front-End |
| url | https://www.mdpi.com/2076-3417/11/1/429 |
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