| Summary: | SiC JBSFETs are fabricated using low contact anneal temperature to simultaneously form the ohmic contact to the N+ source region and a Schottky contact at the JBS diode. It is demonstrated in this paper that a larger N+ source contact width can substantially improve the on-resistance and figures-of-merit of SiC power JBSFETs.The analysis, using analytical models supported by TCAD simulations and experimental data, was performed for JBSFETs with three blocking voltage ratings of 600 V, 1200 V, and 1700 V. For a specific contact resistance of 0.8 mΩ-cm2, it was found that the JBSFET specific on-resistance can be reduced by ∼25% by using an optimum N+ source contact width of 3 µm, rather than the conventional 1 µm, for all blocking voltages. The modelling demonstrated a monotonic reduction in the gate-drain capacitance and charge with increase in the N+ source contact width. A reduction of these parameters by 33% was observed when the N+ source contact width was increased to the optimum 3 µm value. Consequently, the high frequency figures-of-merit for the JBSFETs improved by a remarkable 65% with the optimized N+ source contact width of 3 µm compared with the conventional design of 1 µm.
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