The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Abstract The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, inclu...

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Bibliographic Details
Main Authors: Wei Li, Hongxia Liu, Shulong Wang, Shupeng Chen, Qianqiong Wang
Format: Article
Language:English
Published: SpringerOpen 2018-03-01
Series:Nanoscale Research Letters
Subjects:
Online Access:http://link.springer.com/article/10.1186/s11671-018-2483-8