An optimized design of delay-and energy-efficient Booth multiplier
Multipliers are essential computation units in virtually all computing systems, including processors and numerous AI accelerator architectures. This paper presents an optimized architecture for a Booth multiplier, targeting high performance while minimizing energy consumption and area utilization. T...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2024-09-01
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| Series: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S277267112400278X |