Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes

Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes

Abstract High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly p...

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Bibliographic Details
Main Authors: Chi Su, Yi-Pei Tsai, Chrong-Jung Lin, Ya-Chin King
Format: Article
Language:English
Published: SpringerOpen 2020-05-01
Series:Nanoscale Research Letters
Subjects:
Plasma-induced damage
Advanced FinFET technology
Back-end of line
Inter-metal dielectric
Online Access:http://link.springer.com/article/10.1186/s11671-020-03328-7

Internet

http://link.springer.com/article/10.1186/s11671-020-03328-7

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