Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes

Abstract High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly p...

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Main Authors: Chi Su, Yi-Pei Tsai, Chrong-Jung Lin, Ya-Chin King
Format: Article
Language:English
Published: SpringerOpen 2020-05-01
Series:Nanoscale Research Letters
Subjects:
Online Access:http://link.springer.com/article/10.1186/s11671-020-03328-7
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author Chi Su
Yi-Pei Tsai
Chrong-Jung Lin
Ya-Chin King
author_facet Chi Su
Yi-Pei Tsai
Chrong-Jung Lin
Ya-Chin King
author_sort Chi Su
collection DOAJ
description Abstract High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly proposed test patterns for evaluating the effect of plasma-induced charging effect on the integrity of IMD between closely placed metal lines. Strong correlations between the plasma charging intensities and damages found in IMD layers are found and analyzed comprehensively.
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spelling doaj.art-c5f37579d9c740299df0877a132796602023-08-02T04:15:00ZengSpringerOpenNanoscale Research Letters1556-276X2020-05-011511710.1186/s11671-020-03328-7Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL ProcessesChi Su0Yi-Pei Tsai1Chrong-Jung Lin2Ya-Chin King3Institute of Electronics Engineering, National Tsing Hua UniversityInstitute of Electronics Engineering, National Tsing Hua UniversityInstitute of Electronics Engineering, National Tsing Hua UniversityInstitute of Electronics Engineering, National Tsing Hua UniversityAbstract High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly proposed test patterns for evaluating the effect of plasma-induced charging effect on the integrity of IMD between closely placed metal lines. Strong correlations between the plasma charging intensities and damages found in IMD layers are found and analyzed comprehensively.http://link.springer.com/article/10.1186/s11671-020-03328-7Plasma-induced damageAdvanced FinFET technologyBack-end of lineInter-metal dielectric
spellingShingle Chi Su
Yi-Pei Tsai
Chrong-Jung Lin
Ya-Chin King
Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes
Nanoscale Research Letters
Plasma-induced damage
Advanced FinFET technology
Back-end of line
Inter-metal dielectric
title Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes
title_full Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes
title_fullStr Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes
title_full_unstemmed Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes
title_short Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes
title_sort test pattern design for plasma induced damage on inter metal dielectric in finfet cu beol processes
topic Plasma-induced damage
Advanced FinFET technology
Back-end of line
Inter-metal dielectric
url http://link.springer.com/article/10.1186/s11671-020-03328-7
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